Please refer to FIG. 1, which depicts a circuit diagram of a memory unit in a dynamic random access memory (DRAM) module. The memory unit includes a transistor 11 and a capacitor 12. The capacitor 12 is fully charged if the data value stored in the memory unit is 1, and the capacitor 12 is discharged if the data value is 0. The electric charges accumulated in the capacitor 12 will be progressively lost while reading data. Moreover, charge loss of the capacitor 12 occurs after a period of time despite no access. Therefore, the charge should be refreshed several times in a second. Generally speaking, the entire DRAM module should be refreshed once about every 64 ms to keep the data accurate.
Please refer now to FIG. 2, which depicts a functional block diagram of a conventional computer system. The conventional computer system includes a central processing unit (CPU) 20, a Northbridge chip 21, a Southbridge chip 22 and a DRAM module 23 connected to the Northbridge chip 21 via a bus 210. Nowadays, most computer systems enter a suspend mode in which the CPU 20 stores some necessary data to the DRAM module 23 through the bus 210 after the computer system idles for a period of time. Then the CPU 20, the Northbridge chip 21 and the Southbridge chip 22 are all powered down while only the DRAM module 23 remains powered on, which is called as “suspend to RAM.” Meanwhile, since all other chips are powered down, the DRAM module 23 has to refresh data by using a clock generator (not shown) of its own, i.e. self-refresh.
The leakage current of the capacitor varies with temperature, for example, high temperature results in increased leakage current, which may cause data error since a great deal of charges in the capacitor are lost before the data are refreshed. Therefore, a thermo sensor (not shown) is integrated into the electrically erasable programmable read only memory (EEPROM) 230 of the DRAM module 23 to monitor the temperature in the DRAM module 23 any time. When the computer system has entered a power-saving mode to have all the other chips powered down, the DRAM module 23 can still react to the temperature change. For example, the self-refresh rate is increased in response to the rise in temperature to avoid data error, and the self-refresh rate is decreased in response to the drop in temperature to effectively reduce power consumption. In the prior art, no method has ever provided for effectively adjusting the refresh rate of the DRAM module 23 according to the temperature change when the computer system is in a normal mode. Hence, data error probably occurs in the DRAM module 23 when working in the normal mode. For this reason, the present invention is provided to overcome such disadvantage of the prior art.